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1999 data sheet description the m pd780031ay, 780032ay, 780033ay, and 780034ay are members of the m pd780034ay subseries of the 78k/0 series. this is a m pd780034a subseries product with an added multimaster-supporting i 2 c bus interface, and is suitable for av equipment applications. a flash memory version, the m pd78f0034ay, that can operate in the same power supply voltage range as the mask rom version, and various development tools, are available. detailed function descriptions are provided in the following users manuals. be sure to read them before designing. m pd780024a, 780034a, 780024ay, 780034ay subseries user's manual: u14046e 78k/0 series users manual instructions: u12326e features ? internal rom and ram item program memory data memory package part number (internal rom) (internal high-speed ram) m pd780031ay 8 kbytes 512 bytes ? 64-pin plastic shrink dip (750 mils) m pd780032ay 16 kbytes ? 64-pin plastic qfp (14 14 mm) m pd780033ay 24 kbytes 1024 bytes ? 64-pin plastic lqfp (12 12 mm) m pd780034ay 32 kbytes ? external memory expansion space: 64 kbytes ? minimum instruction execution time: 0.24 m s (@ f x = 8.38-mhz operation) ? i/o ports: 51 (5-v-tolerant n-ch open-drain: 4) ? 10-bit resolution a/d converter: 8 channels (av dd = 1.8 to 5.5 v) ? serial interface: 3 channels (multimaster-supporting i 2 c bus mode, uart mode, 3-wire serial i/o mode) ? timer: 5 channels ? power supply voltage: v dd = 1.8 to 5.5 v applications telephones, home electric appliances, pagers, av equipment, car audios, office automation equipment, etc. 8-bit single-chip microcontrollers document no. u14045ej1v0ds00 (1st edition) date published august 1999 n cp(k) printed in japan mos integrated circuit m pd780031ay, 780032ay, 780033ay, 780034ay the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. not all devices/types available in every country. please check with local nec representative for availability and additional information.
2 m pd780031ay, 780032ay, 780033ay, 780034ay data sheet u14045ej1v0ds00 ordering information part number package m pd780031aycw- 64-pin plastic shrink dip (750 mils) m pd780031aygc- -ab8 64-pin plastic qfp (14 14 mm) m pd780031aygk- -8a8 64-pin plastic lqfp (12 12 mm) m pd780032aycw- 64-pin plastic shrink dip (750 mils) m pd780032aygc- -ab8 64-pin plastic qfp (14 14 mm) m pd780032aygk- -8a8 64-pin plastic lqfp (12 12 mm) m pd780033aycw- 64-pin plastic shrink dip (750 mils) m pd780033aygc- -ab8 64-pin plastic qfp (14 14 mm) m pd780033aygk- -8a8 64-pin plastic lqfp (12 12 mm) m pd780034aycw- 64-pin plastic shrink dip (750 mils) m pd780034aygc- -ab8 64-pin plastic qfp (14 14 mm) m pd780034aygk- -8a8 64-pin plastic lqfp (12 12 mm) remark indicates rom code suffix.
3 m pd780031ay, 780032ay, 780033ay, 780034ay data sheet u14045ej1v0ds00 78k/0 series lineup the products in the 78k/0 series are listed below. the names enclosed in boxes are subseries names. 64-pin 64-pin 80-pin 80-pin 80-pin pd780034a pd780988 pd780034ay m m m 64-pin 64-pin pd780078 pd780078y m m emi-noise reduced version of the pd78054 m pd78018f with added uart and d/a converter and enhanced i/o m pd780024a with increased ram capacity m pd780024a with enhanced a/d converter m on-chip inverter control circuit and uart. emi-noise reduced. pd78044h pd780232 80-pin 80-pin pd78064 pd780841 pd78064b pd780308 100-pin 100-pin 100-pin pd780308y pd78064y 80-pin 78k/0 series for panel control. on-chip fip c/d. display output total: 53 lcd drive basic subseries for driving lcds, on-chip uart bus interface supported call id supported m m m m m m m 80-pin on-chip call id and simple dtmf. emi-noise reduced. m pd78064 with enhanced sio, and increased rom, ram capacity. m emi-noise reduced version of the pd78064 m pd78083 pd78018f pd78018fy pd78014h m emi-noise reduced version of the pd78018f basic subseries for control on-chip uart, capable of operating at low voltage (1.8 v) m m m m 42/44-pin 64-pin 64-pin m a pd780034a with added timer and enhanced serial i/o pd78018f with enhanced serial i/o m 80-pin m pd78054 with enhanced serial i/o 100-pin 100-pin products in mass production products under development y subseries products are compatible with i 2 c bus. 100-pin m pd78078y with enhanced serial i/o and limited functions pd78054 with added timer and enhanced external interface m rom-less version of the pd78078 m 100-pin emi-noise reduced version of the pd78078 m inverter control pd780228 100-pin m m pd780208 100-pin fip tm drive m pd78044f with enhanced i/o and fip c/d. display output total: 53 m pd78044h with enhanced i/o and fip c/d. display output total: 48 m pd780208 m pd78098b m pd78054 with iebus tm controller added. emi-noise reduced. m 100-pin pd780024a pd780024ay m m 80-pin 100-pin pd780958 pd780955 m m ultra low-power consumption. on-chip uart. 80-pin pd780973 m on-chip automobile meter controller/driver 80-pin pd780824 m for automobile meter. on-chip d-can controller. for industrial meter control meter control pd78044f 80-pin basic subseries for driving fip. display output total: 34 m pd78044f with added n-ch open drain i/o. display output total: 34 m 80-pin pd780701y on-chip d-can/iebus controller m 80-pin pd780833y on-chip controller compliant with j1850 (class 2) m pd780948 on-chip d-can controller m pd780065 m pd78054 pd78058f m m pd780058 m pd78070a pd78078 m m control pd78075b m pd78054y pd78058fy m m pd780058y m pd78070ay pd78078y pd780018ay m m m
4 m pd780031ay, 780032ay, 780033ay, 780034ay data sheet u14045ej1v0ds00 the major functional differences among the y subseries are shown below. function rom capacity configuration of serial interface i/o v dd min. subseries name value control m pd78078y 48 k to 60 k 3-wire/2-wire/i 2 c: 1 ch 88 1.8 v 3-wire with automatic transmit/receive function: 1 ch m pd78070ay 3-wire/uart: 1 ch 61 2.7 v m pd780018ay 48 k to 60 k 3-wire with automatic transmit/receive function: 1 ch 88 time-division 3-wire: 1 ch i 2 c bus (multimaster supported): 1 ch m pd780058y 24 k to 60 k 3-wire/2-wire/i 2 c: 1 ch 68 1.8 v 3-wire with automatic transmit/receive function: 1 ch 3-wire/time-division uart: 1 ch m pd78058fy 48 k to 60 k 3-wire/2-wire/i 2 c: 1 ch 69 2.7 v 3-wire with automatic transmit/receive function: 1 ch m pd78054y 16 k to 60 k 3-wire/uart: 1 ch 2.0 v m pd780078y 48 k to 60 k 3-wire: 1 ch 52 1.8 v uart: 1 ch 3-wire/uart: 1 ch i 2 c bus (multimaster supported): 1 ch m pd780034ay 8 k to 32 k uart: 1 ch 51 1.8 v 3-wire: 1 ch m pd780024ay i 2 c bus (multimaster supported): 1 ch m pd78018fy 8 k to 60 k 3-wire/2-wire/i 2 c: 1 ch 53 3-wire with automatic transmit/receive function: 1 ch lcd m pd780308y 48 k to 60 k 3-wire/2-wire/i 2 c: 1 ch 57 2.0 v drive 3-wire/time-division uart: 1 ch 3-wire: 1 ch m pd78064y 16 k to 32 k 3-wire/2-wire/i 2 c: 1 ch 3-wire/uart: 1 ch remark functions other than the serial interface are common to the non-y subseries.
5 m pd780031ay, 780032ay, 780033ay, 780034ay data sheet u14045ej1v0ds00 overview of functions part number m pd780031ay m pd780032ay m pd780033ay m pd780034ay item internal rom 8 kbytes 16 kbytes 24 kbytes 32 kbytes memory high-speed ram 512 bytes 1024 bytes memory space 64 kbytes general-purpose registers 8 bits 32 registers (8 bits 8 registers 4 banks) minimum instruction execution on-chip minimum instruction execution time cycle variable function when main system 0.24 m s/0.48 m s/0.95 m s/1.91 m s/3.81 m s (@ 8.38-mhz operation) clock selected when subsystem 122 m s (@ 32.768-khz operation) clock selected instruction set ? 16-bit operation ? multiply/divide (8 bits 8 bits,16 bits ? 8 bits) ? bit manipulation (set, reset, test, boolean operation) ? bcd adjust, etc. i/o ports total: 51 ? cmos input: 8 ? cmos i/o: 39 ? 5-v-tolerant n-ch open-drain i/o: 4 a/d converter ? 10-bit resolution x 8 channels ? low-voltage operation available: av dd = 1.8 to 5.5 v serial interface ? 3-wire serial i/o mode: 1 channel ? uart mode: 1 channel ? i 2 c bus mode (multimaster supported): 1 channel timer ? 16-bit timer/event counter: 1 channel ? 8-bit timer/event counter: 2 channels ? watch timer: 1 channel ? watchdog timer: 1 channel timer output 3 (8-bit pwm output capable: 2) clock output ? 65.5 khz, 131 khz, 262 khz, 524 khz, 1.05 mhz, 2.10 mhz, 4.19 mhz, 8.38 mhz (@ 8.38-mhz operation with main system clock ) ? 32.768 khz (@ 32.768-khz operation with subsystem clock) buzzer output 1.02 khz, 2.05 khz, 4.10 khz, 8.19 khz (@ 8.38-mhz operation with main system clock) vectored maskable internal: 13, external: 5 interrupt non-maskable internal: 1 sources software 1 power supply voltage v dd = 1.8 to 5.5 v operating ambient temperature t a = C40 to +85 c package ? 64-pin plastic shrink dip (750 mils) ? 64-pin plastic qfp (14 14 mm) ? 64-pin plastic lqfp (12 12 mm) time
6 m pd780031ay, 780032ay, 780033ay, 780034ay data sheet u14045ej1v0ds00 contents 1. pin configuration (top view) ..................................................................................................... 7 2. block diagram .............................................................................................................................10 3. pin functions ............................................................................................................................... .11 3.1 port pins ............................................................................................................................... ..................... 11 3.2 non-port pins ............................................................................................................................... ............. 12 3.3 pin i/o circuits and recommended connection of unused pins ..................................................... 14 4. memory space ............................................................................................................................... 16 5. peripheral hardware function features .......................................................................17 5.1 ports ............................................................................................................................... ............................ 17 5.2 clock generator ............................................................................................................................... ......... 18 5.3 timer/counter ............................................................................................................................... ............ 19 5.4 clock output/buzzer output control circuit ....................................................................................... 23 5.5 a/d converter ............................................................................................................................... ............ 24 5.6 serial interface ............................................................................................................................... ........... 25 6. interrupt function ....................................................................................................................28 7. external device expansion function ...............................................................................31 8. standby function .......................................................................................................................31 9. reset function ............................................................................................................................31 10. mask option ............................................................................................................................... ....31 11. instruction set ...........................................................................................................................32 12. electrical specifications ......................................................................................................34 13. package drawings .....................................................................................................................57 14. recommended soldering conditions ................................................................................60 appendix a. development tools ................................................................................................62 appendix b. related documents ............................................................................................... 65
7 m pd780031ay, 780032ay, 780033ay, 780034ay data sheet u14045ej1v0ds00 1. pin configuration (top view) ? 64-pin plastic shrink dip (750 mils) m pd780031aycw- , 780032aycw- , 780033aycw- , 780034aycw- cautions 1. connect the ic (internally connected) pin directly to v ss0 or v ss1 . 2. connect the av ss pin to v ss0 . remark when the m pd780031ay, 780032ay, 780033ay, and 780034ay are used in applications where the noise generated inside the microcontroller needs to be reduced, the implementation of noise reduction measures, such as supplying voltage to v dd0 and v dd1 individually and connecting v ss0 and v ss1 to different ground lines, is recommended. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 p67/astb p66/wait p65/wr p64/rd p75/buz p74/pcl p73/ti51/to51 p72/ti50/to50 p71/ti01 p70/ti00/to0 p03/intp3/adtrg p02/intp2 p01/intp1 p00/intp0 v ss1 x1 x2 ic xt1 xt2 reset av dd av ref p10/ani0 p11/ani1 p12/ani2 p13/ani3 p14/ani4 p15/ani5 p16/ani6 p17/ani7 av ss 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 p40/ad0 p41/ad1 p42/ad2 p43/ad3 p44/ad4 p45/ad5 p46/ad6 p47/ad7 p50/a8 p51/a9 p52/a10 p53/a11 p54/a12 p55/a13 p56/a14 p57/a15 v ss0 v dd0 p30 p31 p32/sda0 p33/scl0 p34 p35 p36 p20/si30 p21/so30 p22/sck30 p23/rxd0 p24/txd0 p25/asck0 v dd1
8 m pd780031ay, 780032ay, 780033ay, 780034ay data sheet u14045ej1v0ds00 ? 64-pin plastic qfp (14 14 mm) m pd780031aygc- - ab8, 780032aygc- -ab8, 780033aygc- -ab8, 780034aygc- -ab8 ? 64-pin plastic lqfp (12 12 mm) m pd780031aygk- -8a8, 780032aygk- -8a8, 780033aygk- -8a8, 780034aygk- -8a8 cautions 1. connect the ic (internally connected) pin directly to v ss0 or v ss1 . 2. connect the av ss pin to v ss0 . remark when the m pd780031ay, 780032ay, 780033ay, and 780034ay are used in applications where the noise generated inside the microcontroller needs to be reduced, the implementation of noise reduction measures, such as supplying voltage to v dd0 and v dd1 individually and connecting v ss0 and v ss1 to different ground lines, is recommended. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 p50/a8 p51/a9 p52/a10 p53/a11 p54/a12 p55/a13 p56/a14 p57/a15 v ss0 v dd0 p30 p31 p32/sda0 p33/scl0 p34 p35 p36 p20/si30 p21/so30 p22/sck30 p23/rxd0 p24/txd0 p25/asck0 v dd1 av ss p17/ani7 p16/ani6 p15/ani5 p14/ani4 p13/ani3 p12/ani2 p11/ani1 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 p71/ti01 p70/ti00/to0 p03/intp3/adtrg p02/intp2 p01/intp1 p00/intp0 v ss1 x1 x2 ic xt1 xt2 reset av dd av ref p10/ani0 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 p47/ad7 p46/ad6 p45/ad5 p44/ad4 p43/ad3 p42/ad2 p41/ad1 p40/ad0 p67/astb p66/wait p65/wr p64/rd p75/buz p74/pcl p73/ti51/to51 p72/ti50/to50
9 m pd780031ay, 780032ay, 780033ay, 780034ay data sheet u14045ej1v0ds00 p70 to p75: port 7 pcl: programmable clock rd: read strobe reset: reset rxd0: receive data sck30, scl0: serial clock sda0: serial data si30: serial input so30: serial output ti00, ti01, ti50, ti51: timer input to0, to50, to51: timer output txd0: transmit data v dd0 , v dd1 : power supply v ss0 , v ss1 : ground wait: wait wr: write strobe x1, x2: crystal (main system clock) xt1, xt2: crystal (subsystem clock) a8 to a15: address bus ad0 to ad7: address/data bus adtrg: ad trigger input ani0 to ani7: analog input asck0: asynchronous serial clock astb: address strobe av dd : analog power supply av ref : analog reference voltage av ss : analog ground buz: buzzer clock ic: internally connected intp0 to intp3: external interrupt input p00 to p03: port 0 p10 to p17: port 1 p20 to p25: port 2 p30 to p36: port 3 p40 to p47: port 4 p50 to p57: port 5 p64 to p67: port 6
10 m pd780031ay, 780032ay, 780033ay, 780034ay data sheet u14045ej1v0ds00 2. block diagram remark the internal rom and ram capacities differ depending on the product. ti00/to0/p70 16-bit timer/ event counter serial interface 30 interrupt control buzzer output clock output control 78k/0 cpu core port 0 port 1 port 2 port 3 port 4 port 5 port 6 port 7 p70 to p75 p64 to p67 p50 to p57 p40 to p47 p30 to p36 p20 to p25 p10 to p17 p00 to p03 external access system control reset x1 x2 xt1 xt2 rd/p64 wr/p65 wait/p66 astb/p67 ad0/p40 to ad7/p47 a8/p50 to a15/p57 rom ram a/d converter v dd0 v dd1 v ss0 v ss1 ic watchdog timer watch timer 8-bit timer/ event counter 50 8-bit timer/ event counter 51 ti50/to50/p72 ti51/to51/p73 si30/p20 so30/p21 sck30/p22 av dd av ss av ref buz/p75 pcl/p74 ani0/p10 to ani7/p17 intp0/p00 to intp3/p03 ti01/p71 i 2 c bus sda0/p32 scl0/p33 uart0 rxd0/p23 txd0/p24 asck0/p25
11 m pd780031ay, 780032ay, 780033ay, 780034ay data sheet u14045ej1v0ds00 3. pin functions 3.1 port pins (1/2) pin name i/o function after alternate reset function p00 i/o port 0 input intp0 p01 4-bit input/output port intp1 p02 input/output can be specified in 1-bit units. intp2 p03 an on-chip pull-up resistor can be connected by means of software. intp3/adtrg p10 to p17 input port 1 input ani0 to ani7 8-bit input-only port p20 i/o port 2 input si30 p21 6-bit input/output port so30 p22 input/output can be specified in 1-bit units. sck30 p23 an on-chip pull-up resistor can be connected by means of software. rxd0 p24 txd0 p25 asck0 p30 i/o port 3 n-ch open-drain input/output port input p31 7-bit input/output port the mask option can be used to specify the p32 input/output can be connection of an on-chip pull-up resistor to p30, p31. sda0 p33 specified in 1-bit units. leds can be driven directly. scl0 p34 an on-chip pull-up resistor can be p35 connected by means of software. p36 p40 to p47 i/o port 4 input ad0 to ad7 8-bit input/output port input/output can be specified in 1-bit units. an on-chip pull-up resistor can be connected by means of software. the interrupt request flag (krif) is set to 1 by falling edge detection. p50 to p57 i/o port 5 input a8 to a15 8-bit input/output port leds can be driven directly. input/output can be specified in 1-bit units. an on-chip pull-up resistor can be connected by means of software. p64 i/o port 6 input rd p65 4-bit input/output port wr p66 input/output can be specified in 1-bit units. wait p67 an on-chip pull-up resistor can be connected by means of software. astb
12 m pd780031ay, 780032ay, 780033ay, 780034ay data sheet u14045ej1v0ds00 3.1 port pins (2/2) pin name i/o function after alternate reset function p70 i/o port 7 input ti00/to0 p71 6-bit input/output port ti01 p72 input/output can be specified in 1-bit units. ti50/to50 p73 an on-chip pull-up resistor can be connected by means of software. ti51/to51 p74 pcl p75 buz 3.2 non-port pins (1/2) pin name i/o function after alternate reset function intp0 input external interrupt request input for which the valid edge (rising edge, input p00 intp1 falling edge, or both rising and falling edges) can be specified p01 intp2 p02 intp3 p03/adtrg si30 input serial interface serial data input input p20 so30 output serial interface serial data output input p21 sda0 i/o serial interface serial data input/output input p32 sck30 i/o serial interface serial clock input/output input p22 scl0 p33 rxd0 input serial data input for asynchronous serial interface input p23 txd0 output serial data output for asynchronous serial interface input p24 asck0 input serial clock input for asynchronous serial interface input p25 ti00 input external count clock input to 16-bit timer (tm0) input p70/to0 capture trigger input to capture register (cr01) of 16-bit timer (tm0) ti01 capture trigger input to capture register (cr00) of 16-bit timer (tm0) p71 ti50 external count clock input to 8-bit timer (tm50) p72/to50 ti51 external count clock input to 8-bit timer (tm51) p73/to51 to0 output 16-bit timer (tm0) output input p70/ti00 to50 8-bit timer (tm50) output (also used for 8-bit pwm output) input p72/ti50 to51 8-bit timer (tm51) output (also used for 8-bit pwm output) p73/ti51 pcl output clock output (for trimming of main system clock and subsystem clock) input p74 buz output buzzer output input p75 ad0 to ad7 i/o lower address/data bus for expanding memory externally input p40 to p47 a8 to a15 output higher address bus for expanding memory externally input p50 to p57 rd output strobe signal output for reading from external memory input p64 wr strobe signal output for writing to external memory p65 wait input wait insertion at external memory access input p66 astb output strobe output that externally latches address information output to input p67 ports 4 and 5 to access external memory
13 m pd780031ay, 780032ay, 780033ay, 780034ay data sheet u14045ej1v0ds00 3.2 non-port pins (2/2) pin name i/o function after alternate reset function ani0 to ani7 input a/d converter analog input input p10 to p17 adtrg input a/d converter trigger signal input input p03/intp3 av ref input a/d converter reference voltage input av dd a/d converter analog power supply. set potential to that of v dd0 or v dd1 . av ss a/d converter ground potential. set potential to that of v ss0 or v ss1 . reset input system reset input x1 input connecting crystal resonator for main system clock oscillation x2 xt1 input connecting crystal resonator for subsystem clock oscillation xt2 v dd0 positive power supply for ports v ss0 ground potential of ports v dd1 positive power supply (except ports) v ss1 ground potential (except ports) ic internally connected. connect directly to v ss0 or v ss1 .
14 m pd780031ay, 780032ay, 780033ay, 780034ay data sheet u14045ej1v0ds00 3.3 pin i/o circuits and recommended connection of unused pins the input/output circuit type of each pin and recommended connection of unused pins are shown in table 3-1. for the input/output circuit configuration of each type, see figure 3-1. table 3-1. types of pin input/output circuits pin name input/output i/o recommended connection of unused pins circuit type p00/intp0 to p02/intp2 8-c input independently connect to v ss0 via a resistor. p03/intp3/adtrg p10/ani0 to p17/ani7 25 input independently connect to v dd0 or v ss0 via a resistor. p20/si30 8-c i/o p21/so30 5-h p22/sck30 8-c p23/rxd0 p24/txd0 5-h p25/asck0 8-c p30, p31 13-q i/o independently connect to v dd0 via a resistor. p32/sda0 13-r p33/scl0 p34 8-c independently connect to v dd0 or v ss0 via a resistor. p35 5-h p36 8-c p40/ad0 to p47/ad7 5-h i/o independently connect to v dd0 via a resistor. p50/a8 to p57/a15 i/o independently connect to v dd0 or v ss0 via a resistor. p64/rd i/o p65/wr p66/wait p67/astb p70/ti00/to0 8-c p71/ti01 p72/ti50/to50 p73/ti51/to51 p74/pcl 5-h p75/buz reset 2 input xt1 16 connect to v dd0 . xt2 leave open. av dd connect to v dd0 . av ref connect to v ss0 . av ss ic connect directly to v ss0 or v ss1 .
15 m pd780031ay, 780032ay, 780033ay, 780034ay data sheet u14045ej1v0ds00 figure 3-1. pin input/output circuits type 2 schmitt-triggered input with hysteresis characteristics in type 8-c data output disable p-ch in/out v dd0 n-ch p-ch v dd0 pullup enable type 5-h data output disable p-ch in/out v dd0 n-ch input enable p-ch v dd0 pullup enable type 13-q data output disable in/out n-ch v dd0 mask option ? ? ? ? type 13-r input enable v ss0 type 25 v ss0 v ss0 data output disable in/out n-ch v ss0 p-ch feedback cut-off xt1 xt2 type 16 input enable comparator + p-ch n-ch v ref (threshold voltage) v ss0 in
16 m pd780031ay, 780032ay, 780033ay, 780034ay data sheet u14045ej1v0ds00 4. memory space figure 4-1 shows the memory map of the m pd780031ay, 780032ay, 780033ay, and 780034ay. figure 4-1. memory map note the internal rom and internal high-speed ram capacities differ depending on the product (see the following table). part number last address of internal rom start address of internal high-speed ram nnnnh mmmmh m pd780031ay 1fffh fd00h m pd780032ay 3fffh m pd780033ay 5fffh fb00h m pd780034ay 7fffh special function registers (sfrs) 256 8 bits general-purpose registers 32 8 bits internal high-speed ram note reserved external memory internal rom note data memory space program memory space ffffh ff00h feffh fee0h fedfh mmmmh mmmmh ?1 f7ffh nnnnh + 1 nnnnh 0000h program area callf entry area program area callt table area vector table area nnnnh 1000h 0fffh 0800h 07ffh 0080h 007fh 0040h 003fh 0000h f800h
17 m pd780031ay, 780032ay, 780033ay, 780034ay data sheet u14045ej1v0ds00 5. peripheral hardware function features 5.1 ports the following 3 types of i/o ports are available. ? cmos input (port 1): 8 ? cmos input/output (ports 0, 2 to 7, p34 to p36): 39 ? n-ch open-drain input/output (p30 to p33): 4 total: 51 table 5-1. port functions name pin name function port 0 p00 to p03 i/o port pins. input/output can be specified in 1-bit units. an on-chip pull-up resistor can be connected by means of software. port 1 p10 to p17 dedicated input port pins. port 2 p20 to p25 i/o port pins. input/output can be specified in 1-bit units. an on-chip pull-up resistor can be connected by means of software. port 3 p30 to p33 n-ch open-drain i/o port pins. input/output can be specified in 1-bit units. the mask option can be used to specify the connection of an on-chip pull-up resistor to p30, p31. leds can be driven directly. p34 to p36 i/o port pins. input/output can be specified in 1-bit units. an on-chip pull-up resistor can be connected by means of software. port 4 p40 to p47 i/o port pins. input/output can be specified in 1-bit units. an on-chip pull-up resistor can be connected by means of software. the interrupt request flag (krif) is set to 1 by falling edge detection. port 5 p50 to p57 i/o port pins. input/output can be specified in 1-bit units. an on-chip pull-up resistor can be connected by means of software. leds can be driven directly. port 6 p64 to p67 i/o port pins. input/output can be specified in 1-bit units. an on-chip pull-up resistor can be connected by means of software. port 7 p70 to p75 i/o port pins. input/output can be specified in 1-bit units. an on-chip pull-up resistor can be connected by means of software.
18 m pd780031ay, 780032ay, 780033ay, 780034ay data sheet u14045ej1v0ds00 5.2 clock generator a system clock generator is incorporated. the minimum instruction execution time can be changed. ? 0.24 m s/0.48 m s/0.95 m s/1.91 m s/3.81 m s (@ 8.38-mhz operation with main system clock) ? 122 m s (@ 32.768-khz operation with subsystem clock) figure 5-1. clock generator block diagram xt1 xt2 x1 x2 f xt f x subsystem clock oscillator watch timer, clock output function prescaler main system clock oscillator clock to peripheral hardware cpu clock (f cpu ) standby control circuit wait control circuit 2 f x 2 2 f x 2 3 f x 2 4 f x f xt 2 prescaler selector stop 2 1
19 m pd780031ay, 780032ay, 780033ay, 780034ay data sheet u14045ej1v0ds00 5.3 timer/counter five timer/counter channels are incorporated. ? 16-bit timer/event counter: 1 channel ? 8-bit timer/event counter: 2 channels ? watch timer: 1 channel ? watchdog timer: 1 channel table 5-2. operations of timer/event counters 16-bit timer/ 8-bit timer/ watch timer watchdog timer event counter tm0 event counters tm50, tm51 operation mode interval timer 1 channel 2 channels 1 channel note 1 1 channel note 2 external event counter 1 channel 2 channels function timer output 1 output 2 outputs ppg output 1 output pwm output 2 outputs pulse width measurement 2 inputs square wave output 1 output 2 outputs one-shot pulse output 1 output interrupt source 2 2 2 1 notes 1. the watch timer can perform both watch timer and interval timer functions at the same time. 2. the watchdog timer has watchdog timer and interval timer functions. however, use the watchdog timer by selecting either the watchdog timer function or the interval timer function.
20 m pd780031ay, 780032ay, 780033ay, 780034ay data sheet u14045ej1v0ds00 figure 5-2. block diagram of 16-bit timer/event counter tm0 internal bus ti01/p71 f x f x /2 2 f x /2 6 f x /2 3 ti00/to0/p70 16-bit capture/compare register 01 (cr01) match match 16-bit timer counter 0 (tm0) clear noise elimi- nation circuit inttm00 to0/ti00/p70 inttm01 internal bus selector 16-bit capture/compare register 00 (cr00) selector selector selector noise elimi- nation circuit noise elimi- nation circuit output control circuit
21 m pd780031ay, 780032ay, 780033ay, 780034ay data sheet u14045ej1v0ds00 figure 5-3. block diagram of 8-bit timer/event counter tm50 figure 5-4. block diagram of 8-bit timer/event counter tm51 internal bus 8-bit compare register 50 (cr50) ti50/to50/p72 f x /2 4 f x /2 6 f x /2 8 f x /2 10 f x f x /2 2 match mask circuit ovf clear 3 selector tcl502 tcl501 tcl500 timer clock select register 50 (tcl50) internal bus tce50 tmc506 tmc504 lvs50 lvr50 tmc501 toe50 invert level 8-bit timer mode control register 50 (tmc50) s r s q r inv selector inttm50 to50/ti50/p72 selector 8-bit timer counter 50 (tm50) selector internal bus ti51/to51/p73 f x /2 3 f x /2 5 f x /2 7 f x /2 9 f x /2 11 f x /2 match mask circuit ovf clear 3 tcl512 tcl511 tcl510 timer clock select register 51 (tcl51) internal bus tce51 tmc516 tmc514 lvs51 lvr51 tmc511 toe51 invert level 8-bit timer mode control register 51 (tmc51) s r q r inv selector inttm51 to51/ti51/p73 selector selector selector 8-bit compare register 51 (cr51) 8-bit timer counter 51 (tm51) s
22 m pd780031ay, 780032ay, 780033ay, 780034ay data sheet u14045ej1v0ds00 figure 5-5. watch timer block diagram figure 5-6. watchdog timer block diagram f x /2 7 f xt f w f w 2 4 f w 2 5 f w 2 6 f w 2 7 f w 2 8 f w 2 9 clear 9-bit prescaler clear 5-bit counter intwt intwti wtm7 wtm6 wtm5 wtm4 wtm1 wtm0 watch timer operation mode register (wtm) internal bus selector selector oscillation stabilization time select register (osts) clock input control circuit intwdt reset wdt mode signal 3 osts2 osts1 osts0 wdcs2 wdcs1 wdcs0 internal bus division circuit divided clock selection circuit output control circuit division mode selection circuit run wdtm4 wdtm3 watchdog timer clock select register (wdcs) watchdog timer mode register (wdtm) run f x /2 8
23 m pd780031ay, 780032ay, 780033ay, 780034ay data sheet u14045ej1v0ds00 5.4 clock output/buzzer output control circuit a clock output/buzzer output control circuit (cku) is incorporated. clocks with the following frequencies can be output as clock output. ? 65.5 khz/131 khz/262 khz/524 khz/1.05 mhz/2.10 mhz/4.19 mhz/8.38 mhz (@ 8.38-mhz operation with main system clock) ? 32.768 khz (@ 32.768-khz operation with subsystem clock) clocks with the following frequencies can be output as buzzer output. ? 1.02 khz/2.05 khz/4.10 khz/8.19 khz (@ 8.38-mhz operation with main system clock) figure 5-7. block diagram of clock output/buzzer output control circuit cku prescaler f x f xt 8 clock control circuit pcl/p74 buz/p75 4 f x to f x /2 7 f x /2 10 to f x /2 13 selector bcs0, bcs1 bzoe cloe bzoe bcs1 bcs0 cloe ccs3 ccs2 ccs1 ccs0 internal bus clock output select register (cks) selector
24 m pd780031ay, 780032ay, 780033ay, 780034ay data sheet u14045ej1v0ds00 5.5 a/d converter an a/d converter consisting of eight 10-bit resolution channels is incorporated. the following two a/d conversion operation start-up methods are available. ? hardware start ? software start figure 5-8. a/d converter block diagram tap selector intad av dd intp3 internal bus av ref a/d conversion result register 0 (adcr0) control circuit succesive approximation register (sar) edge detection circuit ani0/p10 ani1/p11 ani2/p12 ani3/p13 ani4/p14 ani5/p15 ani6/p16 ani7/p17 adtrg/intp3/p03 selector sample & hold circuit voltage comparator series resistor string edge detection circuit av ss
25 m pd780031ay, 780032ay, 780033ay, 780034ay data sheet u14045ej1v0ds00 5.6 serial interface three serial interface channels are incorporated. ? serial interface uart0: 1 channel ? serial interface sio30: 1 channel ? serial interface iic0: 1 channel (1) serial interface uart0 the serial interface uart0 has two modes: asynchronous serial interface (uart) mode and infrared data transfer mode. ? asynchronous serial interface (uart) mode this mode enables full-duplex operation wherein one byte of data starting from the start bit is transmitted and received. the on-chip uart-dedicated baud-rate generator enables communication using a wide range of selectable baud rates. in addition, a baud rate can be also defined by dividing the clock input to the asck0 pin. the uart-dedicated baud-rate generator can also be used to generate a midi-standard baud rate (31.25 kbps). ? infrared data transfer mode this mode enables pulse output and pulse reception in data format. this mode can be used for office equipment applications such as personal computers. figure 5-9. block diagram of serial interface uart0 internal bus asynchronous serial interface mode register 0 (asim0) asynchronous serial interface status register 0 (asis0) receive buffer register 0 rxb0 rxd0/p23 txd0/p24 receive shift register 0 pe0 fe0 ove0 txs0 intser0 intst0 baud rate generator f x /2 to f x /2 7 txe0 rxe0 ps01 ps00 cl0 sl0 isrm0 irdam0 intsr0 receive control circuit (parity check) transmit shift register 0 transmit control circuit (parity addition) rx0 asck0/p25
26 m pd780031ay, 780032ay, 780033ay, 780034ay data sheet u14045ej1v0ds00 (2) serial interface sio30 the serial interface sio30 has one mode: 3-wire serial i/o mode. ? 3-wire serial i/o mode (fixed as msb first) this is an 8-bit data transfer mode using three lines: a serial clock line (sck30), serial output line (so30), and serial input line (si30). since simultaneous transmit and receive operations are enabled in the 3-wire serial i/o mode, the processing time for data transfer is reduced. the first bit in 8-bit data in the serial transfer is fixed as msb. the 3-wire serial i/o mode is useful for connection to peripheral i/o devices, display controllers, etc. that include a clocked serial interface. figure 5-10. block diagram of serial interface sio30 internal bus 8 serial clock control circuit serial clock counter interrupt request signal generator selector serial i/o shift register 30 (sio30) si30/p20 so30/p21 sck30/p22 intcsi30 f x /2 3 f x /2 4 f x /2 5
27 m pd780031ay, 780032ay, 780033ay, 780034ay data sheet u14045ej1v0ds00 (3) serial interface iic0 the serial interface iic0 has the i 2 c (inter ic) bus mode (multimaster supported). ?i 2 c bus mode (multimaster supported) this is an 8-bit data transfer mode using two lines: a serial clock line (scl0) and serial data bus line (sda0). this mode complies with the i 2 c bus format, and can output "start condition", "data", and "stop condition" during transmission via the serial data bus. this data is automatically detected by hardware during reception. since the scl0 and sda0 are open-drain outputs in iic0, pull-up resistors for the serial clock line and the serial data bus line are required. figure 5-11. block diagram of serial interface iic0 internal bus iic status register 0 (iics0) iic control register 0 (iicc0) slave address register 0 (sva0) noise elimination circuit noise elimination circuit matched signal iic shift register 0 (iic0) so0 latch iice0 d set clear cl00 sda0/p32 scl0/p33 n-ch open- drain output data hold time correction circuit acknowledge detection circuit wake-up control circuit acknowledge detection circuit stop condition detection circuit serial clock counter interrupt request signal generator serial clock control circuit n-ch open-drain output serial clock wait control circuit prescaler intiic0 f x cld0 iic transfer clock select register 0 (iiccl0) internal bus lrel0 wrel0 spie0 wtim0 acke0 stt0 spt0 msts0 ald0 exc0 coi0 trc0 ackd0 std0 spd0 start condition detection circuit dad0 smc0 dfc0 cl00
28 m pd780031ay, 780032ay, 780033ay, 780034ay data sheet u14045ej1v0ds00 6. interrupt function a total of 20 interrupt sources are provided, divided into the following three types. ? non-maskable: 1 ? maskable: 18 ? software: 1 table 6-1. interrupt source list interrupt default interrupt source internal/ vector table type priority note 1 name trigger external address non- intwdt watchdog timer overflow (with watchdog timer internal 0004h (a) maskable mode 1 selected) maskable 0 intwdt watchdog timer overflow (with interval timer (b) mode selected) 1 intp0 pin input edge detection external 0006h (c) 2 intp1 0008h 3 intp2 000ah 4 intp3 000ch 5 intser0 generation of serial interface uart0 internal 000eh (b) reception error 6 intsr0 end of serial interface uart0 reception 0010h 7 intst0 end of serial interface uart0 transmission 0012h 8 intcsi30 end of serial interface sio30 transfer 0014h 9 intiic0 end of serial interface iic0 transfer 0016h 10 intwti reference time interval signal from watch timer 001ah 11 inttm00 matching of tm0 and cr00 (when cr00 is 001ch specified as a compare register) detection of ti01 pin valid edge (when cr00 is specified as a capture register) 12 inttm01 matching of tm0 and cr01 (when cr01 is 001eh specified as a compare register) detection of ti00 pin valid edge (when cr00 is specified as a capture register) 13 inttm50 matching of tm50 and cr50 0020h 14 inttm51 matching of tm51 and cr51 0022h 15 intad0 end of conversion by a/d converter 0024h 16 intwt watch timer overflow 0026h 17 intkr detection of port 4 falling edge external 0028h (d) software brk execution of brk instruction 003eh (e) notes 1. default priority is the priority order when several maskable interrupt requests are generated at the same time. 0 is the highest and 17 is the lowest. 2. basic configuration types (a) to (e) correspond to (a) to (e) in figure 6-1. basic configuration type note 2
29 m pd780031ay, 780032ay, 780033ay, 780034ay data sheet u14045ej1v0ds00 figure 6-1. basic configuration of interrupt function (1/2) (a) internal non-maskable interrupt (b) internal maskable interrupt (c) external maskable interrupt (intp0 to intp3) internal bus priority control circuit vector table address generator standby release signal interrupt request mk internal bus ie pr isp if priority control circuit vector table address generator standby release signal interrupt request mk ie pr isp if priority control circuit vector table address generator external interrupt edge enable register (egp, egn) edge detection circuit internal bus standby release signal interrupt request
30 m pd780031ay, 780032ay, 780033ay, 780034ay data sheet u14045ej1v0ds00 figure 6-1. basic configuration of interrupt function (2/2) (d) external maskable interrupt (intkr) (e) software interrupt if: interrupt request flag ie: interrupt enable flag isp: in-service priority flag mk: interrupt mask flag pr: priority specification flag mem: memory expansion mode register mk ie pr isp if priority control circuit vector table address generator falling edge detection circuit internal bus standby release signal interrupt request 1 when mem = 01h priority control circuit vector table address generator internal bus interrupt request
31 m pd780031ay, 780032ay, 780033ay, 780034ay data sheet u14045ej1v0ds00 7. external device expansion function the external device expansion function is for connecting external devices to areas other than the internal rom, ram, and sfr. ports 4 to 6 are used for external device connection. 8. standby function the following two standby modes are available for further reduction of system current consumption. ? halt mode: in this mode, the cpu operation clock is stopped. the average current consumption can be reduced by intermittent operation by combining this mode with the normal operation mode. ? stop mode: in this mode, oscillation of the main system clock is stopped. all the operations performed on the main system clock are suspended, and only the subsystem clock is used, resulting in extremely small power consumption. this can be used only when the main system clock is operating (the subsystem clock oscillation cannot be stopped). figure 8-1. standby function 9. reset function the following two reset methods are available. ? external reset by reset signal input ? internal reset by watchdog timer runaway time detection 10. mask option table 10.1 pin mask option selection pins mask option p30, p31 an on-chip pull-up resistor can be specified in 1-bit units. the mask option can be used to specify the connection of an on-chip pull-up resistor to p30, p31, in 1-bit units. main system clock operation stop mode main system clock operation is stopped interrupt request interrupt request halt instruction halt instruction interrupt request stop instruction css = 1 css = 0 subsystem clock operation halt mode halt mode clock supply for cpu is stopped, oscillation is maintained clock supply for cpu is stopped, oscillation is maintained
32 m pd780031ay, 780032ay, 780033ay, 780034ay data sheet u14045ej1v0ds00 11. instruction set (1) 8-bit instructions mov, xch, add, addc, sub, subc, and, or, xor, cmp, mulu, divuw, inc, dec, ror, rol, rorc, rolc, ror4, rol4, push, pop, dbnz 2nd operand 1st operand #byte a r note sfr saddr !addr16 psw [de] [hl] [hl + byte] [hl + b] [hl + c] $addr16 1 none a r add addc sub subc and or xor cmp mov mov mov mov mov mov mov mov ror xch xch xch xch xch xch xch rol add add add add add rorc addc addc addc addc addc rolc sub sub sub sub sub subc subc subc subc subc and and and and and or or or or or xor xor xor xor xor cmp cmp cmp cmp cmp mov mov add addc sub subc and or xor cmp inc dec b, c sfr mov mov dbnz mov add addc sub subc and or xor cmp saddr mov dbnz inc dec !addr16 mov psw mov mov push pop [de] ror4 mov [hl] mov rol4 [hl + byte] [hl + b] [hl + c] mov x c mulu divuw note except r = a
33 m pd780031ay, 780032ay, 780033ay, 780034ay data sheet u14045ej1v0ds00 (2) 16-bit instructions movw, xchw, addw, subw, cmpw, push, pop, incw, decw 2nd operand 1st operand ax rp sfrp saddrp !addr16 sp #word addw subw cmpw movw movw movw movw ax movw note movw movw movw movw movw rp note xchw sfrp movw saddrp movw !addr16 movw sp movw none incw, decw push, pop 2nd operand 1st operand a.bit sfr.bit saddr.bit psw.bit [hl].bit cy $addr16 none a.bit sfr.bit saddr.bit psw.bit [hl].bit cy mov1 mov1 mov1 mov1 mov1 bt bf btclr bt bf btclr bt bf btclr bt bf btclr bt bf btclr set1 clr1 set1 clr1 set1 clr1 set1 clr1 set1 clr1 set1 clr1 not1 mov1 and1 or1 xor1 mov1 and1 or1 xor1 mov1 and1 or1 xor1 mov1 and1 or1 xor1 mov1 and1 or1 xor1 2nd operand 1st operand ax !addr16 !addr11 [addr5] $addr16 basic instruction compound instruction br call br callf callt br, bc, bnc bz, bnz bt, bf btclr dbnz note only when rp = bc, de or hl (3) bit manipulation instructions mov1, and1, or1, xor1, set1, clr1, not1, bt, bf, btclr (4) call instructions/branch instructions call, callf, callt, br, bc, bnc, bz, bnz, bt, bf, btclr, dbnz (5) other instructions adjba, adjbs, brk, ret, reti, retb, sel, nop, ei, di, halt, stop
34 m pd780031ay, 780032ay, 780033ay, 780034ay data sheet u14045ej1v0ds00 12. electrical specifications absolute maximum ratings (t a = 25 c) parameter symbol test conditions ratings unit supply voltage v dd C0.3 to +6.5 v av dd C0.3 to v dd + 0.3 note v av ref C0.3 to v dd + 0.3 note v av ss C0.3 to +0.3 v input voltage v i1 p00 to p03, p10 to p17, p20 to p25, p34 to p36, p40 to p47, C0.3 to v dd + 0.3 note v p50 to p57, p64 to p67, p70 to p75, x1, x2, xt1, xt2, reset v i2 p30 to p33 n-ch open-drain without pull-up resistor C0.3 to +6.5 v with pull-up resistor C0.3 to v dd + 0.3 note v output voltage v o C0.3 to v dd + 0.3 note v analog input voltage v an p10 to p17 analog input pin av ss C 0.3 to av ref + 0.3 note v and C0.3 to v dd + 0.3 note output current, i oh per pin C10 ma high total for p00 to p03, p40 to p47, p50 to p57, p64 to p67, p70 to p75 C15 ma total for p20 to p25, p30 to p36 C15 ma output current, i ol per pin for p00 to p03, p20 to p25, p34 to 20 ma low p36, p40 to p47, p64 to p67, p70 to p75 per pin for p30 to p33, p50 to p57 30 ma total for p00 to p03, p40 to p47, 50 ma p64 to p67, p70 to p75 total for p20 to p25 20 ma total for p30 to p36 100 ma total for p50 to p57 100 ma operating ambient t a C40 to +85 c temperature storage t stg C65 to +150 c temperature note 6.5 v or below caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded.
35 m pd780031ay, 780032ay, 780033ay, 780034ay data sheet u14045ej1v0ds00 resonator recommended parameter test conditions min. typ. max. unit circuit ceramic oscillation v dd = 4.0 to 5.5 v 1.0 8.38 mhz resonator frequency (f x ) note 1 1.0 5.0 oscillation after v dd reaches 4 ms stabilization time note 2 oscillation voltage range min. crystal oscillation v dd = 4.0 to 5.5 v 1.0 8.38 mhz resonator frequency (f x ) note 1 1.0 5.0 oscillation v dd = 4.0 to 5.5 v 10 ms stabilization time note 2 30 external x1 input v dd = 4.0 to 5.5 v 1.0 8.38 mhz clock frequency (f x ) note 1 1.0 5.0 x1 input v dd = 4.0 to 5.5 v 50 500 ns high-/low-level width 85 500 (t xh , t xl ) capacitance (t a = 25 c , v dd = v ss = 0 v) parameter symbol test conditions min. typ. max. unit input c in f = 1 mhz 15 pf capacitance unmeasured pins returned to 0 v. i/o c io f = 1 mhz p00 to p03, p20 to p25, 15 pf capacitance unmeasured pins p34 to p36, p40 to p47, returned to 0 v. p50 to p57, p64 to p67, p70 to p75 p30 to p33 20 pf remark unless otherwise specified, the characteristics of alternate-function pins are the same as those of port pins. main system clock oscillator characteristics (t a = C40 to 85 c, v dd = 1.8 to 5.5 v) notes 1. indicates only oscillator characteristics. refer to ac characteristics for instruction execution time. 2. time required to stabilize oscillation after reset or stop mode release. cautions 1. when using the main system clock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. ? keep the wiring length as short as possible. ? do not cross the wiring with the other signal lines. ? do not route the wiring near a signal line through which a high fluctuating current flows. ? always make the ground point of the oscillator capacitor the same potential as v ss1 . ? do not ground the capacitor to a ground pattern through which a high current flows. ? do not fetch signals from the oscillator. 2. when the main system clock is stopped and the system is operating on the subsystem clock, wait until the oscillation stabilization time has been secured by the program before switching back to the main system clock. c2 x1 x2 ic c1 c2 x1 x2 ic c1 x2 x1 pd74hcu04 m
36 m pd780031ay, 780032ay, 780033ay, 780034ay data sheet u14045ej1v0ds00 subsystem clock oscillator characteristics (t a = C40 to +85 c, v dd = 1.8 to 5.5 v) notes 1. indicates only oscillator characteristics. refer to ac characteristics for instruction execution time. 2. time required to stabilize oscillation after v dd reaches oscillation voltage range min. cautions 1. when using the subsystem clock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. ? keep the wiring length as short as possible. ? do not cross the wiring with the other signal lines. ? do not route the wiring near a signal line through which a high fluctuating current flows. ? always make the ground point of the oscillator capacitor the same potential as v ss1 . ? do not ground the capacitor to a ground pattern through which a high current flows. ? do not fetch signals from the oscillator. 2. the subsystem clock oscillator is designed as a low-amplitude circuit for reducing current consumption, and is more prone to malfunction due to noise than the main system clock oscillator. particular care is therefore required with the wiring method when the subsystem clock is used. min. 32 32 resonator crystal resonator external clock parameter oscillation frequency (f xt ) note 1 oscillation stabilization time note 2 xt1 input frequency (f xt ) note 1 xt1 input high-/low-level width (t xth , t xtl ) test conditions typ. 32.768 1.2 max. 35 2 10 38.5 unit khz s khz v dd = 4.0 to 5.5 v recommended circuit 515 c3 xt2 xt1 ic r c4 xt1 xt2 m pd74hcu04 m s
37 m pd780031ay, 780032ay, 780033ay, 780034ay data sheet u14045ej1v0ds00 recommended oscillator constant main system clock: ceramic resonator (t a = C40 to +85 c) manufacturer part number frequency recommended circuit constant oscillation voltage range (mhz) c1 (pf) c2 (pf) min. (v) max. (v) murata mfg. csb1000j 1.00 100 100 1.8 5.5 co., ltd. csa2.00mg040 2.00 100 100 1.8 5.5 cst2.00mg040 2.00 on-chip on-chip 1.8 5.5 csa3.58mg 3.58 30 30 1.8 5.5 cst3.58mgw 3.58 on-chip on-chip 1.8 5.5 csa4.19mg 4.19 30 30 1.8 5.5 cst4.19mgw 4.19 on-chip on-chip 1.8 5.5 csa5.00mg 5.00 30 30 1.8 5.5 cst5.00mgw 5.00 on-chip on-chip 1.8 5.5 csa8.00mtz 8.00 30 30 4.0 5.5 cst8.00mtw 8.00 on-chip on-chip 4.0 5.5 csa8.00mtz093 8.00 30 30 4.0 5.5 cst8.00mtw093 8.00 on-chip on-chip 4.0 5.5 csa8.38mtz 8.38 30 30 4.0 5.5 cst8.38mtw 8.38 on-chip on-chip 4.0 5.5 csa8.38mtz093 8.38 30 30 4.0 5.5 cst8.38mtw093 8.38 on-chip on-chip 4.0 5.5 tdk ccr3.58mc3 3.58 on-chip on-chip 1.8 5.5 ccr4.19mc3 4.19 on-chip on-chip 1.8 5.5 ccr5.0mc3 5.00 on-chip on-chip 1.8 5.5 ccr8.0mc5 8.00 on-chip on-chip 4.0 5.5 ccr8.38mc5 8.38 on-chip on-chip 4.0 5.5 caution the oscillator constant and oscillation voltage range indicate conditions of stable oscillation. oscillation frequency precision is not guaranteed. for applications requiring oscillation frequency precision, the oscillation frequency must be adjusted on the implementation circuit. for details, please contact directly the manufacturer of the resonator you will use.
38 m pd780031ay, 780032ay, 780033ay, 780034ay data sheet u14045ej1v0ds00 dc characteristics (t a = C40 to +85 c, v dd = 1.8 to 5.5 v) parameter symbol test conditions min. typ. max. unit output current, i oh per pin C1 ma high all pins C15 ma output current, i ol per pin for p00 to p03, p20 to p25, p34 to p36, 10 ma low p40 to p47, p64 to p67, p70 to p75 per pin for p30 to p33, p50 to p57 15 ma total for p00 to p03, p40 to p47, p64 to p67, p70 to p75 20 ma total for p20 to p25 10 ma total for p30 to p36 70 ma total for p50 to p57 70 ma input voltage, v ih1 p10 to p17, p21, p24, p35, v dd = 2.7 to 5.5 v 0.7v dd v dd v high p40 to p47, p50 to p57, p64 to p67, p74, p75 0.8v dd v dd v v ih2 p00 to p03, p20, p22, p23, p25, v dd = 2.7 to 5.5 v 0.8v dd v dd v p34, p36, p70 to p73, reset 0.85v dd v dd v v ih3 p30 to p33 v dd = 2.7 to 5.5 v 0.7v dd 5.5 v (n-ch open-drain) 0.8v dd 5.5 v v ih4 x1, x2 v dd = 2.7 to 5.5 v v dd C 0.5 v dd v v dd C 0.2 v dd v v ih5 xt1, xt2 v dd = 4.0 to 5.5 v 0.8v dd v dd v 0.9v dd v dd v input voltage, v il1 p10 to p17, p21, p24, p35, v dd = 2.7 to 5.5 v 0 0.3v dd v low p40 to p47, p50 to p57, p64 to p67, p74, p75 0 0.2v dd v v il2 p00 to p03, p20, p22, p23, p25, v dd = 2.7 to 5.5 v 0 0.2v dd v p34, p36, p70 to p73, reset 0 0.15v dd v v il3 p30 to p33 4.0 v v dd 5.5 v 0 0.3v dd v 2.7 v v dd < 4.0 v 0 0.2v dd v 1.8 v v dd < 2.7 v 0 0.1v dd v v il4 x1, x2 v dd = 2.7 to 5.5 v 0 0.4 v 0 0.2 v v il5 xt1, xt2 v dd = 4.0 to 5.5 v 0 0.2v dd v 0 0.1v dd v output voltage, v oh1 v dd = 4.0 to 5.5 v, i oh = C1 ma v dd C 1.0 v dd v high i oh = C100 m a v dd C 0.5 v dd v output voltage, v ol1 p30 to p33 v dd = 4.0 to 5.5 v, 2.0 v low p50 to p57 i ol = 15 ma 0.4 2.0 v p00 to p03, p20 to p25, p34 to p36, v dd = 4.0 to 5.5 v, 0.4 v p40 to p47, p64 to p67, p70 to p75 i ol = 1.6 ma v ol2 i ol = 400 m a 0.5 v remark unless otherwise specified, the characteristics of alternate-function pins are the same as those of port pins.
39 m pd780031ay, 780032ay, 780033ay, 780034ay data sheet u14045ej1v0ds00 dc characteristics (t a = C40 to +85 c, v dd = 1.8 to 5.5 v) parameter symbol test conditions min. typ. max. unit input leakage i lih1 v in = v dd p00 to p03, p10 to p17, p20 to p25, 3 m a current, high p34 to p36, p40 to p47, p50 to p57, p64 to p67, p70 to p75, reset i lih2 x1, x2, xt1, xt2 20 m a i lih3 v in = 5.5 v p30 to p33 note 3 m a input leakage i lil1 v in = 0 v p00 to p03, p10 to p17, p20 to p25, C3 m a current, low p34 to p36, p40 to p47, p50 to p57, p64 to p67, p70 to p75, reset i lil2 x1, x2, xt1, xt2 C20 m a i lil3 p30 to p33 note C3 m a output leakage i loh v out = v dd 3 m a current, high output leakage i lol v out = 0 v C3 m a current, low mask option r 1 v in = 0 v, 15 30 90 k w pull-up resistance p30, p31 software pull- r 2 v in = 0 v, 15 30 90 k w up resistance p00 to p03, p20 to p25, p34 to p36, p40 to p47, p50 to p57, p64 to p67, p70 to p75 note when pull-up resistors are not connected to p30, p31 (specified by the mask option). remark unless otherwise specified, the characteristics of alternate-function pins are the same as those of port pins.
40 m pd780031ay, 780032ay, 780033ay, 780034ay data sheet u14045ej1v0ds00 dc characteristics (t a = C40 to +85 c, v dd = 1.8 to 5.5 v) parameter symbol test conditions min. typ. max. unit power supply i dd1 8.38-mhz v dd = 5.0v 10% note 2 when a/d converter is 5.5 11 ma current note 1 crystal oscillation stopped operating mode when a/d converter is 6.5 13 ma operating 5.00-mhz v dd = 3.0v 10% note 2 when a/d converter is 2 4 ma crystal oscillation stopped operating mode when a/d converter is 3 6 ma operating v dd = 2.0v 10% note 3 when a/d converter is 0.4 1.5 ma stopped when a/d converter is 1.4 4.2 ma operating i dd2 8.38-mhz v dd = 5.0v 10% note 2 when peripheral functions 1.1 2.2 ma crystal oscillation are stopped halt mode when peripheral functions 4.7 ma are operating 5.00-mhz v dd = 3.0v 10% note 2 when peripheral functions 0.35 0.7 ma crystal oscillation are stopped halt mode when peripheral functions 1.7 ma are operating v dd = 2.0v 10% note 3 when peripheral functions 0.15 0.4 ma are stopped when peripheral functions 1.1 ma are operating i dd3 32.768-khz crystal oscillation v dd = 5.0 v 10% 40 80 m a operating mode note 4 v dd = 3.0 v 10% 20 40 m a v dd = 2.0 v 10% 10 20 m a i dd4 32.768-khz crystal oscillation v dd = 5.0 v 10% 30 60 m a halt mode note 4 v dd = 3.0 v 10% 6 18 m a v dd = 2.0 v 10% 2 10 m a i dd5 xt1 = 0v stop mode v dd = 5.0 v 10% 0.1 30 m a when feedback resistor is not used v dd = 3.0 v 10% 0.05 10 m a v dd = 2.0 v 10% 0.05 10 m a notes 1. total current through the internal power supply (v dd0 , v dd1 ), including the peripheral operation current (except the current through pull-up resistors of ports and the av ref pin). 2. when the processor clock control register (pcc) is set to 00h. 3. when pcc is set to 02h. 4. when main system clock operation is stopped.
41 m pd780031ay, 780032ay, 780033ay, 780034ay data sheet u14045ej1v0ds00 ac characteristics (1) basic operation (t a = C40 to +85 c, v dd = 1.8 to 5.5 v) parameter symbol test conditions min. typ. max. unit cycle time t cy operating with 4.0 v v dd 5.5 v 0.24 16 m s (min. instruction main system clock 2.7 v v dd < 4.0 v 0.4 16 m s execution time) 1.6 16 m s operating with subsystem clock 103.9 note 1 122 125 m s ti00, ti01 input t tih0 , t til0 4.0 v v dd 5.5 v 2/f sam + 0.1 note2 m s high-/low-level 2.7 v v dd < 4.0 v 2/f sam + 0.2 note2 m s width 2/f sam + 0.5 note2 m s ti50, ti51 input f ti5 v dd = 2.7 to 5.5 v 0 4 mhz frequency 0 275 khz ti50, ti51 input t tih5 , t til5 v dd = 2.7 to 5.5 v 100 ns high-/low-level width 1.8 ns interrupt request t inth , t intl intp0 to intp3, v dd = 2.7 to 5.5 v 1 m s input high-/low p40 to p47 -level width 2 m s reset t rsl v dd = 2.7 to 5.5 v 10 m s low-level width 20 m s notes 1. value when an external clock is used. when a crystal resonator is used, it is 114 m s (min.). 2. selection of f sam = f x , f x /4, f x /64 is possible using bits 0 and 1 (prm00, prm01) of prescaler mode register 0 (prm0). however, if the ti00 valid edge is selected as the count clock, the value becomes f sam = f x /8.
42 m pd780031ay, 780032ay, 780033ay, 780034ay data sheet u14045ej1v0ds00 t cy vs. v dd (main system clock operation) 16.0 5.0 1.0 2.0 1.6 0.4 0.24 0.1 supply voltage v dd [v] cycle time t cy [ s] 0 10.0 1.0 2.0 3.0 4.0 5.0 6.0 1.8 5.5 2.7 operation guaranteed range m
43 m pd780031ay, 780032ay, 780033ay, 780034ay data sheet u14045ej1v0ds00 (2) read/write operation (t a = C40 to + 85 c, v dd = 4.0 to 5.5 v) (1/3) parameter symbol test conditions min. max. unit astb high-level width t asth 0.3t cy ns address setup time t ads 20 ns address hold time t adh 6ns data input time from address t add1 (2 + 2n)t cy C 54 ns t add2 (3 + 2n)t cy C 60 ns address output time from rd t rdad 0 100 ns data input time from rd t rdd1 (2 + 2n)t cy C 87 ns t rdd2 (3 + 2n)t cy C 93 ns read data hold time t rdh 0ns rd low-level width t rdl1 (1.5 + 2n)t cy C 33 ns t rdl2 (2.5 + 2n)t cy C 33 ns wait input time from rd t rdwt1 t cy C 43 ns t rdwt2 t cy C 43 ns wait input time from wr t wrwt t cy C 25 ns wait low-level width t wtl (0.5 + n)t cy + 10 (2 + 2n)t cy ns write data setup time t wds 60 ns write data hold time t wdh 6ns wr low-level width t wrl1 (1.5 + 2n)t cy C 15 ns rd delay time from astb t astrd 6ns wr delay time from astb t astwr 2t cy C 15 ns astb - delay time from t rdast 0.8t cy C 15 1.2t cy ns rd - at external fetch address hold time from t rdadh 0.8t cy C 15 1.2t cy + 30 ns rd - at external fetch write data output time from rd - t rdwd 40 ns write data output time from wr t wrwd 10 60 ns address hold time from wr - t wradh 0.8t cy C 15 1.2t cy + 30 ns rd - delay time from wait - t wtrd 0.8t cy 2.5t cy + 25 ns wr - delay time from wait - t wtwr 0.8t cy 2.5t cy + 25 ns remarks 1. t cy = t cy /4 2. n indicates the number of waits. 3 .c l = 100 pf (c l indicates the load capacitance of the ad0 to ad7, a8 to a15, rd, wr, wait, and astb pins.)
44 m pd780031ay, 780032ay, 780033ay, 780034ay data sheet u14045ej1v0ds00 (2) read/write operation (t a = C40 to + 85 c, v dd = 2.7 to 4.0 v) (2/3) parameter symbol test conditions min. max. unit astb high-level width t asth 0.3t cy ns address setup time t ads 30 ns address hold time t adh 10 ns data input time from address t add1 (2 + 2n)t cy C 108 ns t add2 (3 + 2n)t cy C 120 ns address output time from rd t rdad 0 200 ns data input time from rd t rdd1 (2 + 2n)t cy C 148 ns t rdd2 (3 + 2n)t cy C 162 ns read data hold time t rdh 0ns rd low-level width t rdl1 (1.5 + 2n)t cy C 40 ns t rdl2 (2.5 + 2n)t cy C 40 ns wait input time from rd t rdwt1 t cy C 75 ns t rdwt2 t cy C 60 ns wait input time from wr t wrwt t cy C 50 ns wait low-level width t wtl (0.5 + 2n)t cy + 10 (2 + 2n)t cy ns write data setup time t wds 60 ns write data hold time t wdh 10 ns wr low-level width t wrl1 (1.5 + 2n)t cy C 30 ns rd delay time from astb t astrd 10 ns wr delay time from astb t astwr 2t cy C 30 ns astb - delay time from t rdast 0.8t cy C 30 1.2t cy ns rd - at external fetch address hold time from t rdadh 0.8t cy C 30 1.2t cy + 60 ns rd - at external fetch write data output time from rd - t rdwd 40 ns write data output time from wr t wrwd 20 120 ns address hold time from wr - t wradh 0.8t cy C 30 1.2t cy + 60 ns rd - delay time from wait - t wtrd 0.5t cy 2.5t cy + 50 ns wr - delay time from wait - t wtwr 0.5t cy 2.5t cy + 50 ns remarks 1. t cy = t cy /4 2. n indicates the number of waits. 3. c l = 100 pf (c l indicates the load capacitance of the ad0 to ad7, ad8 to ad15, rd, wr, wait, and astb pins.)
45 m pd780031ay, 780032ay, 780033ay, 780034ay data sheet u14045ej1v0ds00 (2) read/write operation (t a = C40 to + 85 c, v dd = 1.8 to 2.7 v) (3/3) parameter symbol test conditions min. max. unit astb high-level width t asth 0.3t cy ns address setup time t ads 120 ns address hold time t adh 20 ns data input time from address t add1 (2 + 2n)t cy C 233 ns t add2 (3 + 2n)t cy C 240 ns address output time from rd t rdad 0 400 ns data input time from rd t rdd1 (2 + 2n)t cy C 325 ns t rdd2 (3 + 2n)t cy C 332 ns read data hold time t rdh 0ns rd low-level width t rdl1 (1.5 + 2n)t cy C 92 ns t rdl2 (2.5 + 2n)t cy C 92 ns wait input time from rd t rdwt1 t cy C 350 ns t rdwt2 t cy C 132 ns wait input time from wr t wrwt t cy C 100 ns wait low-level width t wtl (0.5 + 2n)t cy + 10 (2 + 2n)t cy ns write data setup time t wds 60 ns write data hold time t wdh 20 ns wr low-level width t wrl1 (1.5 + 2n)t cy C 60 ns rd delay time from astb t astrd 20 ns wr delay time from astb t astwr 2t cy C 60 ns astb - delay time from t rdast 0.8t cy C 60 1.2t cy ns rd - at external fetch address hold time from t rdadh 0.8t cy C 60 1.2t cy + 120 ns rd - at external fetch write data output time from rd - t rdwd 40 ns write data output time from wr t wrwd 40 240 ns address hold time from wr - t wradh 0.8t cy C 60 1.2t cy + 120 ns rd - delay time from wait - t wtrd 0.5t cy 2.5t cy + 100 ns wr - delay time from wait - t wtwr 0.5t cy 2.5t cy + 100 ns remarks 1. t cy = t cy /4 2. n indicates the number of waits. 3. c l = 100pf (c l indicates the load capacitance of the ad0 to ad7, ad8 to ad15, rd, wr, wait, and astb pins.)
46 m pd780031ay, 780032ay, 780033ay, 780034ay data sheet u14045ej1v0ds00 (3) serial interface (t a = C40 to + 85 c, v dd = 1.8 to 5.5 v) (a) 3-wire serial i/o mode (sck30 ... internal clock output) parameter symbol test conditions min. typ. max. unit sck30 cycle time t kcy1 4.0 v v dd 5.5 v 954 ns 2.7 v v dd < 4.0 v 1600 ns 3200 ns sck30 high-/low-level t kh1 , t kl1 v dd = 4.0 to 5.5 v t kcy1 /2 C 50 ns width t kcy1 /2 C 100 ns si30 setup time t sik1 4.0 v v dd 5.5v 100 ns (to sck30 - ) 2.7 v v dd < 4.0v 150 ns 300 ns si30 hold time t ksi1 400 ns (from sck30 - ) so30 output t kso1 c = 100 pf note 300 ns delay time from sck30 note c is the load capacitance of the sck30 and so30 output lines. (b) 3-wire serial i/o mode (sck30 ... external clock input) parameter symbol test conditions min. typ. max. unit sck30 cycle time t kcy2 4.0 v v dd 5.5 v 800 ns 2.7 v v dd < 4.0 v 1600 ns 3200 ns sck30 high-/low-level t kh2 , t kl2 4.0 v v dd 5.5 v 400 ns width 2.7 v v dd < 4.0 v 800 ns 1600 ns si30 setup time t sik2 100 ns (to sck30 - ) si30 hold time t ksi2 400 ns (from sck30 - ) so30 output t kso2 c = 100 pf note 300 ns delay time from sck30 note c is the load capacitance of the so30 output line.
47 m pd780031ay, 780032ay, 780033ay, 780034ay data sheet u14045ej1v0ds00 (c) uart mode (dedicated baud-rate generator output) parameter symbol test conditions min. typ. max. unit transfer rate 4.0 v v dd 5.5 v 131031 bps 2.7 v v dd < 4.0 v 78125 bps 39063 bps (d) uart mode (external clock input) parameter symbol test conditions min. typ. max. unit asck0 cycle time t kcy3 4.0 v v dd 5.5 v 800 ns 2.7 v v dd < 4.0 v 1600 ns 3200 ns asck0 high-/low-level width t kh3 , 4.0 v v dd 5.5 v 400 ns t kl3 2.7 v v dd < 4.0 v 800 ns 1600 ns transfer rate 4.0 v v dd 5.5 v 39063 bps 2.7 v v dd < 4.0 v 19531 bps 9766 bps (e) uart mode (infrared ray data transfer mode) parameter symbol test conditions min. max. unit transfer rate v dd = 4.0 to 5.5 v 131031 bps bit rate allowable error v dd = 4.0 to 5.5 v 0.87 % output pulse width v dd = 4.0 to 5.5 v 1.2 0.24/fbr note m s input pulse width v dd = 4.0 to 5.5 v 4/f x m s note fbr: specified baud rate
48 m pd780031ay, 780032ay, 780033ay, 780034ay data sheet u14045ej1v0ds00 (f) i 2 c bus mode parameter symbol standard mode high-speed mode unit min. max. min. max. scl0 clock frequency f clk 0 100 0 400 khz bus-free time t buf 4.7 1.3 m s (between stop and start condition) hold time note 1 t hd:sta 4.0 0.6 m s scl0 clock low-level width t low 4.7 1.3 m s scl0 clock high-level width t high 4.0 0.6 m s start/restart condition setup time t su:sta 4.7 0.6 m s data hold time cbus compatible master t hd:dat 5.0 m s i 2 c bus 0 note 2 0 note 2 0.9 note 3 m s data setup time t su:dat 250 100 note 4 ns sda0 and scl0 signal rise time t r 1000 20 + 0.1cb note 5 300 ns sda0 and scl0 signal fall time t f 300 20 + 0.1cb note 5 300 ns stop condition setup time t su:sto 4.0 0.6 m s spike pulse width controlled by input filter t sp 0 50ns capacitive load per bus line cb 400 400 pf notes 1. in the start condition, the first clock pulse is generated after this hold time. 2. to fill in the undefined area of the scl0 falling edge, it is necessary for the device to internally provide at least 300 ns of hold time for the sda0 signal (which is v ihmin. of the scl0 signal). 3. if the device does not extend the scl0 signal low hold time (t low ), only maximum data hold time t hd:dat needs to be fulfilled. 4. the high-speed mode i 2 c bus is available in a standard mode i 2 c bus system. at this time, the conditions described below must be satisfied. ? if the device does not extend the scl0 signal low state hold time t su:dat 3 250 ns ? if the device extends the scl0 signal low state hold time be sure to transmit the next data bit to the sda0 line before the scl0 line is released (t rmax. + t su:dat = 1000 + 250 = 1250 ns by standard mode i 2 c bus specification). 5. cb: total capacitance per bus line (unit: pf)
49 m pd780031ay, 780032ay, 780033ay, 780034ay data sheet u14045ej1v0ds00 ac timing test points (excluding x1, xt1 inputs) clock timing ti timing t xl t xh 1/f x v ih4 (min.) v il4 (max.) t xtl t xth 1/f xt v ih5 (min.) v il5 (max.) x1 input xt1 input t til0 t tih0 ti00, ti01 0.8v dd 0.2v dd test points 0.8v dd 0.2v dd 1/f ti5 t tih5 t til5 ti50, ti51
50 m pd780031ay, 780032ay, 780033ay, 780034ay data sheet u14045ej1v0ds00 read/write operation external fetch (no wait): external fetch (wait insertion): a8 to a15 ad0 to ad7 astb rd higher 8-bit address lower-8-bit address t add1 hi-z t ads t asth t adh t rdd1 t rdad instruction code t rdadh t rdast t astrd t rdl1 t rdh a8 to a15 ad0 to ad7 astb rd higher 8-bit address lower 8-bit address t add1 hi-z t ads t asth t adh t rdad t rdd1 instruction code t rdadh t rdast t astrd t rdl1 t rdh wait t rdwt1 t wtl t wtrd
51 m pd780031ay, 780032ay, 780033ay, 780034ay data sheet u14045ej1v0ds00 external data access (no wait): external data access (wait insertion): a8 to a15 ad0 to ad7 astb rd higher 8-bit address lower 8-bit address t add2 hi-z t ads t asth t adh t rdd2 t rdad read data t astrd t rdwd wr t astwr write data hi-z t wdh t wradh t wds t wrwd t wrl1 t rdh t rdl2 a8 to a15 ad0 to ad7 astb rd higher 8-bit address lower 8-bit address t add2 t ads t asth t adh t rdad t rdd2 read data t astrd wr t astwr write data hi-z t wdh t wradh t wds t wrwd t wrl1 t rdh t rdl2 t rdwt2 t wtl t wrwt t wtl t wtwr t wtrd wait t rdwd hi-z
52 m pd780031ay, 780032ay, 780033ay, 780034ay data sheet u14045ej1v0ds00 serial transfer timing 3-wire serial i/o mode: uart mode (external clock input): t kcym t klm t khm sck30 si30 so30 t sikm t ksim t ksom input data output data m = 1, 2 t kcy3 t kh3 t kl3 asck0
53 m pd780031ay, 780032ay, 780033ay, 780034ay data sheet u14045ej1v0ds00 i 2 c bus mode: scl0 sda0 t hd:sta t buf t hd:dat t high t f t su:dat t su:sta t hd:sta t sp t su : sto t r t low stop condition start condition stop condition restart condition
54 m pd780031ay, 780032ay, 780033ay, 780034ay data sheet u14045ej1v0ds00 a/d converter characteristics (t a = C40 to +85 c, v dd = av dd = av ref = 1.8 to 5.5 v, av ss = v ss = 0 v) parameter symbol conditions min. typ. max. unit resolution 10 10 10 bit overall error notes 1, 2 4.0 v av ref 5.5 v 0.2 0.4 %fsr 2.7 v av ref < 4.0 v 0.3 0.6 %fsr 1.8 v av ref < 2.7 v 0.6 1.2 %fsr conversion time t conv 4.0 v av ref 5.5 v 14 96 m s 2.7 v av ref < 4.0 v 19 96 m s 1.8 v av ref < 2.7 v 28 96 m s zero-scale offset notes 1, 2 4.0 v av ref 5.5 v 0.4 %fsr 2.7 v av ref < 4.0 v 0.6 %fsr 1.8 v av ref < 2.7 v 1.2 %fsr full-scale offset notes 1, 2 4.0 v av ref 5.5 v 0.4 %fsr 2.7 v av ref < 4.0 v 0.6 %fsr 1.8 v av ref < 2.7 v 1.2 %fsr integral linearity error note 1 4.0 v av ref 5.5 v 2.5 lsb 2.7 v av ref < 4.0 v 4.5 lsb 1.8 v av ref < 2.7 v 8.5 lsb differential linearity error note 1 4.0 v av ref 5.5 v 1.5 lsb 2.7 v av ref < 4.0 v 2.0 lsb 1.8 v av ref < 2.7 v 3.5 lsb analog input voltage v ian 0av ref v reference voltage av ref 1.8 av dd v resistance between av ref and av ss r ref when a/d conversion is not performed 20 40 k w notes 1. excludes quantization error ( 1/2 lsb). 2. shown as a percentage of the full scale value.
55 m pd780031ay, 780032ay, 780033ay, 780034ay data sheet u14045ej1v0ds00 data memory stop mode low supply voltage data retention characteristics (t a = C40 to +85 c) parameter symbol test conditions min. typ. max. unit data retention power v dddr 1.6 5.5 v supply voltage data retention i dddr v dddr = 1.6 v 0.1 30 m a power supply subsystem clock stop (xt1 = v dd ) and current feed-back resistor disconnected release signal set time t srel 0 m s oscillation stabilization t wait release by reset 2 17 /fx ms time release by interrupt request note ms note selection of 2 12 /f x and 2 14 /f x to 2 17 /f x is possible using bits 0 to 2 (osts0 to osts2) of the oscillation stabilization time select register (osts). data retention timing (stop mode release by reset) t srel t wait v dd reset stop instruction execution stop mode data retention mode internal reset operation halt mode operating mode v dddr
56 m pd780031ay, 780032ay, 780033ay, 780034ay data sheet u14045ej1v0ds00 data retention timing (standby release signal: stop mode release by interrupt request signal) interrupt request input timing reset input timing t srel t wait v dd stop instruction execution stop mode data retention mode halt mode operating mode standby release signal (interrupt request) v dddr intp0 to intp2 intp3 t intl t inth t intl t rsl reset
57 m pd780031ay, 780032ay, 780033ay, 780034ay data sheet u14045ej1v0ds00 13. package drawings remark the external dimensions and materials of the es version are the same as those of the mass-produced version. i j g h f d n m cb m r 64 33 32 1 k l notes 1. controlling dimension millimeter. p64c-70-750a,c-3 item millimeters inches b c d f g h j k 1.778 (t.p.) 3.2 0.3 0.51 min. 1.78 max. l m 0.17 0.25 19.05 (t.p.) 5.08 max. 17.0 0.2 n 0 to 15 0.50 0.10 0.9 min. r 0.070 max. 0.020 0.035 min. 0.126 0.012 0.020 min. 0.200 max. 0.750 (t.p.) 0.669 0.010 0.007 0 to 15 +0.004 ?.003 0.070 (t.p.) +0.10 ?.05 +0.004 ?.005 64 pin plastic shrink dip (750 mil) 2. each lead centerline is located within 0.17 mm (0.007 inch) of its true position (t.p.) at maximum material condition. 3. item "k" to center of leads when formed parallel. a 58.0 2.283 +0.028 ?.008 +0.68 ?.20 i 4.05 0.159 +0.011 ?.008 +0.26 ?.20 a +0.009 ?.008
58 m pd780031ay, 780032ay, 780033ay, 780034ay data sheet u14045ej1v0ds00 remark the external dimensions and materials of the es version are the same as those of the mass-produced version. 64 pin plastic qfp ( 14) item millimeters inches i j 0.8 (t.p.) 0.15 0.006 0.031 (t.p.) a 17.6 0.4 0.693 0.016 b 14.0 0.2 0.551 +0.009 ?.008 c 14.0 0.2 0.551 +0.009 ?.008 d 17.6 0.4 0.693 0.016 f g 1.0 1.0 0.039 0.039 h 0.37 0.015 p64gc-80-ab8-4 l 0.8 0.2 0.031 +0.009 ?.008 m 0.17 0.007 n 0.10 0.004 +0.08 ?.07 +0.08 ?.07 q 0.1 0.1 0.004 0.004 r s 2.85 max. 5 5 5 5 0.113 max. +0.003 ?.004 note 1. controlling dimension millimeter. 2. each lead centerline is located within 0.15 mm (0.006 inch) of its true position (t.p.) at maximum material condition. m q r k m l p g f hi s detail of lead end k 1.8 0.2 0.071 0.008 p 2.55 0.1 0.100 0.004 +0.003 ?.004 48 49 32 64 1 17 16 33 s a b cd j ns
59 m pd780031ay, 780032ay, 780033ay, 780034ay data sheet u14045ej1v0ds00 remark the external dimensions and materials of the es version are the same as those of the mass-produced version. 64 pin plastic lqfp (12x12) item millimeters inches 0.65 (t.p.) j 0.026 k 1.4 0.2 0.055 0.008 f 1.125 1.125 g 0.044 0.044 14.8 0.4 d 0.583 0.016 notes 1. controlling dimension millimeter. 2. each lead centerline is located within 0.13 mm of its true position (t.p.) at maximum material condition. a 14.8 0.4 0.583 0.016 b 12.0 0.2 0.472 c 12.0 0.2 0.472 0.13 i 0.005 h 0.32 0.08 0.013 q r p g l m k hi j f s detail of lead end 0.10 n 0.004 m 0.17 0.007 p 1.4 0.1 0.055 5 5 r5 5 s 1.7 max. 0.067 max. 0.125 0.075 q 0.005 0.003 l 0.6 0.2 0.024 p64gk-65-8a8-2 a b cd m 48 49 32 64 1 17 16 33 s n s + 0.08 - 0.07 + 0.009 - 0.008 + 0.009 - 0.008 + 0.003 - 0.004 + 0.008 - 0.009 + 0.003 - 0.004 + 0.004 - 0.005
60 m pd780031ay, 780032ay, 780033ay, 780034ay data sheet u14045ej1v0ds00 14. recommended soldering conditions this product should be soldered and mounted under the following recommended conditions. for the details of the recommended soldering conditions, refer to the document semiconductor device mounting technology manual (c10535e) . for soldering methods and conditions other than those recommended below, contact your nec sales represen- tative. table 14-1. surface mounting type soldering conditions (1) m pd780031aygc- -ab8: 64-pin plastic qfp (14 14 mm) m pd780032aygc- -ab8: 64-pin plastic qfp (14 14 mm) m pd780033aygc- -ab8: 64-pin plastic qfp (14 14 mm) m pd780034aygc- -ab8: 64-pin plastic qfp (14 14 mm) soldering method soldering conditions recommended condition symbol infrared reflow package peak temperature: 235 c, time: 30 seconds max. ir35-00-3 (at 210 c or higher), count: three times or less vps package peak temperature: 215 c, time: 40 seconds max. vp15-00-3 (at 200 c or higher), count: three times or less wave soldering solder bath temperature: 260 c max., time: 10 seconds max., ws60-00-1 count: once, preheating temperature: 120 c max. (package surface temperature) partial heating pin temperature: 300 c max., time: 3 seconds max. (per pin row) CC caution do not use different soldering methods together (except for partial heating).
61 m pd780031ay, 780032ay, 780033ay, 780034ay data sheet u14045ej1v0ds00 (2) m pd780031aygk- -8a8: 64-pin plastic lqfp (12 12 mm) m pd780032aygk- -8a8: 64-pin plastic lqfp (12 12 mm) m pd780033aygk- -8a8: 64-pin plastic lqfp (12 12 mm) m pd780034aygk- -8a8: 64-pin plastic lqfp (12 12 mm) soldering method soldering conditions recommended condition symbol infrared reflow package peak temperature: 235 c, time: 30 seconds max. ir35-107-2 (at 210 c or higher), count: two times or less, exposure limit: 7 days note (after that, prebake at 125 c for 10 hours) vps package peak temperature: 215 c, time: 40 seconds max. vp15-107-2 (at 200 c or higher), count: two times or less, exposure limit: 7 days note (after that, prebake at 125 c for 10 hours) wave soldering solder bath temperature: 260 c max., time: 10 seconds max., ws60-107-1 count: once, preheating temperature: 120 c max. (package surface temperature), exposure limit: 7 days note (after that, prebake at 125 c for 10 hours ) partial heating pin temperature: 300 c max., time: 3 seconds max. (per pin row) CC note after opening the dry pack, store it at 25 c or less and 65%rh or less for the allowable storage period. caution do not use different soldering methods together (except for partial heating). table 14-2. insertion type soldering conditions m pd780031aycw- : 64-pin plastic shrink dip (750mils) m pd780032aycw- : 64-pin plastic shrink dip (750mils) m pd780033aycw- : 64-pin plastic shrink dip (750mils) m pd780034aycw- : 64-pin plastic shrink dip (750mils) soldering method soldering conditions wave soldering solder bath temperature: 260 c max., time: 10 seconds max. (only for pins) partial heating pin temperature: 300 c max., time: 3 seconds max. (per pin row) caution apply wave soldering only to the pins and be careful not to bring solder into direct contact with the package.
62 m pd780031ay, 780032ay, 780033ay, 780034ay data sheet u14045ej1v0ds00 appendix a. development tools the following development tools are available for system development using the m pd780034ay subseries. also refer to (5) cautions on using development tools. (1) language processing software ra78k/0 assembler package common to 78k/0 series cc78k/0 c compiler package common to 78k/0 series df780034 device file common to m pd780034a subseries cc78k/0-l c compiler library source file common to 78k/0 series (2) flash memory writing tools flashpro ii (fl-pr2) flash programmer dedicated to microcontrollers with on-chip flash memory flashpro iii (fl-pr3, pg-fp3) fa-64cw adapter for flash memory writing fa-64gc fa-64gk (3) debugging tools ? when using in-circuit emulator ie-78k0-ns ie-78k0-ns in-circuit emulator common to 78k/0 series ie-70000-mc-ps-b power supply unit for ie-78k0-ns ie-78k0-ns-pa note performance board to enhance and expand the functions of ie-78k0-ns ie-70000-98-if-c interface adapter when using pc-9800 series as host machine (excluding notebook pcs) (c bus supported) ie-70000-cd-if-a pc card and interface cable when using notebook pc as host machine (pcmcia socket supported) ie-70000-pc-if-c interface adapter when using ibm pc/at tm or compatible as host machine (isa bus supported) ie-70000-pci-if adapter required when using pc in which pci bus is embedded as host machine ie-780034-ns-em1 emulation board to emulate m pd780034ay subseries np-64cw emulation probe for 64-pin plastic shrink dip (cw type) np-64gc emulation probe for 64-pin plastic qfp (gc-ab8 type) np-64gc-tq np-64gk emulation probe for 64-pin plastic lqfp (gk-8a8 type) tgk-064sbw conversion adapter to connect np-64gk and target system board on which a 64-pin plastic lqfp (gk-8a8 type) can be mounted. ev-9200gc-64 socket to be mounted on target system board made for 64-pin plastic qfp (gc-ab8 type) id78k0-ns integrated debugger for ie-78k0-ns sm78k0 system simulator common to 78k/0 series df780034 device file common to m pd780034a subseries note under development
63 m pd780031ay, 780032ay, 780033ay, 780034ay data sheet u14045ej1v0ds00 ? when using in-circuit emulator ie-78001-r-a ie-78001-r-a in-circuit emulator common to 78k/0 series ie-70000-98-if-c interface adapter when using pc-9800 series as host machine (excluding notebook pcs) (c bus supported) ie-70000-pc-if-c interface adapter when using ibm pc/at or compatible as host machine (isa bus supported) ie-70000-pci-if adapter required when using pc in which pci bus is embedded as host machine ie-78000-r-sv3 interface adapter and cable when using ews as host machine ie-780034-ns-em1 emulation board to emulate m pd780034ay subseries ie-78k0-r-ex1 emulation probe conversion board necessary when using ie-780034-ns-em1 on ie-78001-r-a ep-78240cw-r emulation probe for 64-pin plastic shrink dip (cw type) ep-78240gc-r emulation probe for 64-pin plastic qfp (gc-ab8 type) ep-78012gk-r emulation probe for 64-pin plastic lqfp (gk-8a8 type) tgk-064sbw conversion adapter to connect ep-78012gk-r a nd target system board on which a 64-pin plastic lqfp (gk-8a8 type) can be mounted. ev-9200gc-64 socket to be mounted on target system board made for 64-pin plastic qfp (gc-ab8 type) id78k0 integrated debugger for ie-78001-r-a sm78k0 system simulator common to 78k/0 series df780034 device file common to m pd780034a subseries (4) real-time os rx78k/0 real-time os for 78k/0 series mx78k0 os for 78k/0 series
64 m pd780031ay, 780032ay, 780033ay, 780034ay data sheet u14045ej1v0ds00 (5) cautions on using development tools ? the id78k0-ns, id78k0, and sm78k0 are used in combination with the df780034. ? the cc78k/0 and rx78k/0 are used in combination with the ra78k/0 and the df780034. ? fl-pr2, fl-pr3, fa-64cw, fa-64gc, fa-64gk, np-64cw, np-64gc, np-64gc-tq, and np-64gk are products made by naito densei machida mfg. co., ltd. (+81-44-822-3813). contact an nec distributor regarding the purchase of these products. ? the tgk-064sbw is a product made by tokyo eletech corporation. refer to: daimaru kogyo, ltd. tokyo electronic division (+81-3-3820-7112) osaka electronic division (+81-6-6244-6672) ? for third-party development tools, see the 78k/0 series selection guide (u11126e) . ? the host machines and oss supporting each software are as follows. host machine pc ews [os] pc-9800 series [windows tm ] hp9000 series 700 tm [hp-ux tm ] ibm pc/at and compatibles sparcstation tm [sunos tm , solaris tm ] software [japanese/english windows] news tm (risc) [news-os tm ] ra78k/0 ? note ? cc78k/0 ? note ? id78k0-ns ? C id78k0 ?? sm78k0 ? C rx78k/0 ? note ? mx78k0 ? note ? note dos-based software
65 m pd780031ay, 780032ay, 780033ay, 780034ay data sheet u14045ej1v0ds00 appendix b. related documents documents related to devices document name document no. document no. (english) (japanese) m pd780024a, 780034a, 780024ay, 780034ay subseries users manual u14046e u14046j m pd780031ay, 780032ay, 780033ay, 780034ay data sheet this document u14045j m pd78f0034ay data sheet u14041e u14041j 78k/0 series users manual instructions u12326e u12326j 78k/0 series instruction table u10903j 78k/0 series instruction set u10904j documents related to development tools (users manuals) document name document no. document no. (english) (japanese) ra78k0 assembler package operation u11802e u11802j assembly language u11801e u11801j structured assembly language u11789e u11789j ra78k series structured assembler preprocessor eeu-1402 u12323j cc78k0 c compiler operation u11517e u11517j language u11518e u11518j cc78k0 c compiler application note programming know-how u13034e u13034j ie-78k0-ns to be prepared to be prepared ie-78001-r-a to be prepared to be prepared ie-780034-ns-em1 to be prepared to be prepared ep-78240 u10332e eeu-986 ep-78012gk-r eeu-1538 eeu-5012 sm78k0 system simulator windows based reference u10181e u10181j sm78k series system simulator external part user open u10092e u10092j interface specifications id78k0-ns integrated debugger windows based reference u12900e u12900j id78k0 integrated debugger ews based reference u11151j id78k0 integrated debugger pc based reference u11539e u11539j id78k0 integrated debugger windows based guide u11649e u11649j caution the related documents listed above are subject to change without notice. be sure to use the latest version of each document for designing.
66 m pd780031ay, 780032ay, 780033ay, 780034ay data sheet u14045ej1v0ds00 documents related to embedded software (users manuals) document name document no. document no. (english) (japanese) 78k/0 series real-time os basics u11537e u11537j installation u11536e u11536j 78k/0 series os mx78k0 basics u12257e u12257j other related documents document name document no. document no. (english) (japanese) semiconductors selection guide products & packages (cd-rom) x13769x semiconductor device mounting technology manual c10535e c10535j quality grades on nec semiconductor devices c11531e c11531j nec semiconductor device reliability/quality control system c10983e c10983j guide to prevent damage for semiconductor devices by electrostatic discharge (esd) c11892e c11892j guide to microcomputer-related products by third party u11416j caution the related documents listed above are subject to change without notice. be sure to use the latest version of each document for designing.
67 m pd780031ay, 780032ay, 780033ay, 780034ay data sheet u14045ej1v0ds00 [memo]
68 m pd780031ay, 780032ay, 780033ay, 780034ay data sheet u14045ej1v0ds00 notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function. caution purchase of nec i 2 c components conveys a license under the philips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips.
69 m pd780031ay, 780032ay, 780033ay, 780034ay data sheet u14045ej1v0ds00 regional information some information contained in this document may vary from country to country. before using any nec product in your application, piease contact the nec office in your country to obtain a list of authorized representatives and distributors. they will verify: device availability ordering information product release schedule availability of related technical literature development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. nec electronics inc. (u.s.) santa clara, california tel: 408-588-6000 800-366-9782 fax: 408-588-6130 800-729-9288 nec electronics (germany) gmbh duesseldorf, germany tel: 0211-65 03 02 fax: 0211-65 03 490 nec electronics (uk) ltd. milton keynes, uk tel: 01908-691-133 fax: 01908-670-290 nec electronics italiana s.r.l. milano, italy tel: 02-66 75 41 fax: 02-66 75 42 99 nec electronics (germany) gmbh benelux office eindhoven, the netherlands tel: 040-2445845 fax: 040-2444580 nec electronics (france) s.a. velizy-villacoublay, france tel: 01-30-67 58 00 fax: 01-30-67 58 99 nec electronics (france) s.a. spain office madrid, spain tel: 91-504-2787 fax: 91-504-2860 nec electronics (germany) gmbh scandinavia office taeby, sweden tel: 08-63 80 820 fax: 08-63 80 388 nec electronics hong kong ltd. hong kong tel: 2886-9318 fax: 2886-9022/9044 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-528-0303 fax: 02-528-4411 nec electronics singapore pte. ltd. united square, singapore 1130 tel: 65-253-8311 fax: 65-250-3583 nec electronics taiwan ltd. taipei, taiwan tel: 02-2719-2377 fax: 02-2719-5951 nec do brasil s.a. electron devices division rodovia presidente dutra, km 214 07210-902-guarulhos-sp brasil tel: 55-11-6465-6810 fax: 55-11-6465-6829 j99.1
m pd780031ay, 780032ay, 780033ay, 780034ay the export of this product from japan is regulated by the japanese government. to export this product may be prohibited without governmental license, the need for which must be judged by the customer. the export or re-export of this product from a country other than japan may also be prohibited without a license from that country. please call an nec sales representative. the related documents indicated in this publication may include preliminary versions. however, preliminary versions are not marked as such. fip and iebus are trademarks of nec corporation. windows is either a registered trademark or a trademark of microsoft corporation in the united states and/ or other countries. pc/at is a trademark of international business machines corporation. hp9000 series 700 and hp-ux are trademarks of hewlett-packard company. sparcstation is a trademark of sparc international, inc. solaris and sunos are trademarks of sun microsystems, inc. news and news-os are trademarks of sony corporation. the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. descriptions of circuits, software, and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software, and information in the design of the customer's equipment shall be done under the full responsibility of the customer. nec corporation assumes no responsibility for any losses incurred by the customer or third parties arising from the use of these circuits, software, and information. while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. nec devices are classified into the following three quality grades: "standard", "special", and "specific". the specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices is "standard" unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact an nec sales representative in advance. m7 98. 8

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